最近搞了个ARM Cortex A7 SOC的Verilog源码，分享一下Cortex A7部分。
解压密码：123321
综合提示缺少ca7scu_defs.v， 文件内容如下：
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited.
//
// (C) COPYRIGHT 2008-2012 ARM Limited.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited.
//
// SVN Information
//
// Checked In : Date:2012−05−1513:47:05+0100(Tue,15May2012)
//
// Revision : Revision:209348
//
// Release Information : CORTEX-A7-r0p4-00rel0
//
//-----------------------------------------------------------------------------

//-----------------------------------------------------------------------------
// Abstract : SCU block internal definitions
//-----------------------------------------------------------------------------

`ifndef CA7_UNDEFINE

define CA7_MIN_L1D_SIZE (8*1024) define CA7_MAX_L1D_SIZE (64*1024)

define CA7_MIN_L2_SIZE (128*1024) define CA7_MAX_L2_SIZE (1024*1024)

define CA7_L1D_SIZE_W log2(CA7_MAX_L1D_SIZE/CA7_MIN_L1D_SIZE)

define CA7_L2_SIZE_W log2(CA7_MAX_L2_SIZE/CA7_MIN_L2_SIZE)

define CA7_SCU_ADDR_W 40 define CA7_SCU_CPU_RDATA_W 128
define CA7_SCU_CPU_WDATA_W 256 define CA7_SCU_CPU_CDDATA_W 256
`define CA7_SCU_EXT_DATA_W 128

`define CA7_SCU_LINE_LENGTH 64 // bytes

define CA7_SCU_L1D_ASSOC 4 define CA7_SCU_L2_ASSOC 8

`define CA7_SCU_NUM_LFBS 3

define CA7_SCU_MAX_OUTSTANDING_DVM 63 define CA7_SCU_NUM_WRITE_TOKENS 16

define CA7_SCU_CPU_WSTRB_W (CA7_SCU_CPU_WDATA_W/8)
define CA7_SCU_EXT_STRB_W (CA7_SCU_EXT_DATA_W/8)

define CA7_SCU_BYTES_IN_DR_BEAT (CA7_SCU_CPU_RDATA_W/8)
define CA7_SCU_DR_BEATS_IN_LINE (CA7_SCU_LINE_LENGTH/CA7_SCU_BYTES_IN_DR_BEAT) define CA7_SCU_BYTES_IN_DW_BEAT (CA7_SCU_CPU_WDATA_W/8) define CA7_SCU_DW_BEATS_IN_LINE (CA7_SCU_LINE_LENGTH/CA7_SCU_BYTES_IN_DW_BEAT)
define CA7_SCU_BYTES_IN_CD_BEAT (CA7_SCU_CPU_CDDATA_W/8)
define CA7_SCU_CD_BEATS_IN_LINE (CA7_SCU_LINE_LENGTH/CA7_SCU_BYTES_IN_CD_BEAT) define CA7_SCU_BYTES_IN_EXT_BEAT (CA7_SCU_EXT_DATA_W/8) define CA7_SCU_EXT_BEATS_IN_LINE (CA7_SCU_LINE_LENGTH/CA7_SCU_BYTES_IN_EXT_BEAT)

define CA7_SCU_DR_BEAT_ADDR_L log2(CA7_SCU_BYTES_IN_DR_BEAT) define CA7_SCU_DR_BEAT_ADDR_W (CA7_SCU_ADDR_W-CA7_SCU_DR_BEAT_ADDR_L)
define CA7_SCU_DR_BEAT_ADDR_B CA7_SCU_ADDR_W-1:CA7_SCU_DR_BEAT_ADDR_L define CA7_SCU_DW_BEAT_ADDR_L log2(CA7_SCU_BYTES_IN_DW_BEAT)
define CA7_SCU_DW_BEAT_ADDR_W (CA7_SCU_ADDR_W-CA7_SCU_DW_BEAT_ADDR_L) define CA7_SCU_DW_BEAT_ADDR_B CA7_SCU_ADDR_W-1:CA7_SCU_DW_BEAT_ADDR_L
define CA7_SCU_CD_BEAT_ADDR_L log2(CA7_SCU_BYTES_IN_CD_BEAT) define CA7_SCU_CD_BEAT_ADDR_W (CA7_SCU_ADDR_W-CA7_SCU_CD_BEAT_ADDR_L)
define CA7_SCU_CD_BEAT_ADDR_B CA7_SCU_ADDR_W-1:CA7_SCU_CD_BEAT_ADDR_L define CA7_SCU_EXT_BEAT_ADDR_L log2(CA7_SCU_BYTES_IN_EXT_BEAT)
define CA7_SCU_EXT_BEAT_ADDR_W (CA7_SCU_ADDR_W-CA7_SCU_EXT_BEAT_ADDR_L) define CA7_SCU_EXT_BEAT_ADDR_B CA7_SCU_ADDR_W-1:CA7_SCU_EXT_BEAT_ADDR_L

// Address width inside tagctl/DDI - handles both internal read requests and external snoops
define CA7_SCU_INT_BEAT_ADDR_L min(CA7_SCU_DR_BEAT_ADDR_L,CA7_SCU_EXT_BEAT_ADDR_L)
define CA7_SCU_INT_BEAT_ADDR_W (CA7_SCU_ADDR_W-CA7_SCU_INT_BEAT_ADDR_L) define CA7_SCU_INT_BEAT_ADDR_B CA7_SCU_ADDR_W-1:CA7_SCU_INT_BEAT_ADDR_L

define CA7_SCU_LINE_ADDR_L log2(CA7_SCU_LINE_LENGTH) define CA7_SCU_LINE_ADDR_W (CA7_SCU_ADDR_W-CA7_SCU_LINE_ADDR_L)
define CA7_SCU_LINE_ADDR_B CA7_SCU_ADDR_W-1:`CA7_SCU_LINE_ADDR_L

define CA7_SCU_CPU_SNOOP_ID_W log2(`CA7_SCU_NUM_DDI_CHANS)

define CA7_SCU_CPU_ACADDR_L log2(CA7_SCU_BYTES_IN_CD_BEAT) define CA7_SCU_CPU_ACADDR_W (CA7_SCU_ADDR_W-CA7_SCU_CPU_ACADDR_L)
define CA7_SCU_CPU_ACADDR_B CA7_SCU_ADDR_W-1:`CA7_SCU_CPU_ACADDR_L

define CA7_SCU_CPU_ACLEN_W log2(CA7_SCU_LINE_LENGTH/(CA7_SCU_CPU_CDDATA_W/8))

define CA7_SCU_PERIPH_DW_OFFSET_B CA7_SCU_DW_BEAT_ADDR_L-1:log2(CA7_SCU_PERIPH_DATA_W/8)
define CA7_SCU_EXT_DW_OFFSET_B CA7_SCU_DW_BEAT_ADDR_L-1:log2(CA7_SCU_EXT_DATA_W/8)

define CA7_SCU_CPU_DW_OFFSET_L (min(log2(CA7_SCU_PERIPH_DATA_W/8),log2(CA7_SCU_EXT_DATA_W/8)))

define CA7_SCU_LINE_DATA_W (CA7_SCU_LINE_LENGTH*8)

define CA7_SCU_L1D_INDEX_H (log2(CA7_MAX_L1D_SIZE/CA7_SCU_L1D_ASSOC)-1)
define CA7_SCU_L1D_INDEX_W (CA7_SCU_L1D_INDEX_H-CA7_SCU_LINE_ADDR_L+1) define CA7_SCU_L1D_INDEX_B CA7_SCU_L1D_INDEX_H:CA7_SCU_LINE_ADDR_L

define CA7_SCU_L1D_TAG_L log2(CA7_MIN_L1D_SIZE/CA7_SCU_L1D_ASSOC)
define CA7_SCU_L1D_TAG_W (CA7_SCU_ADDR_W-CA7_SCU_L1D_TAG_L) define CA7_SCU_L1D_TAG_B CA7_SCU_ADDR_W-1:CA7_SCU_L1D_TAG_L

define CA7_SCU_L1D_WAY_W log2(`CA7_SCU_L1D_ASSOC)

define CA7_SCU_L1D_TAGRAM_ADDR_W CA7_SCU_L1D_INDEX_W
define CA7_SCU_L1D_TAGRAM_DATA_W (CA7_SCU_L1D_TAG_W+3)

define CA7_SCU_L1D_TAGRAM_TAG_B 0+:CA7_SCU_L1D_TAG_W
define CA7_SCU_L1D_TAGRAM_NS_B CA7_SCU_L1D_TAG_W
define CA7_SCU_L1D_TAGRAM_CLSTR_UNIQ_B (CA7_SCU_L1D_TAG_W+1)
define CA7_SCU_L1D_TAGRAM_VALID_B (CA7_SCU_L1D_TAG_W+2)

define CA7_SCU_L2_INDEX_H (log2(CA7_MAX_L2_SIZE/CA7_SCU_L2_ASSOC)-1)
define CA7_SCU_L2_INDEX_W (CA7_SCU_L2_INDEX_H-CA7_SCU_LINE_ADDR_L+1) define CA7_SCU_L2_INDEX_B CA7_SCU_L2_INDEX_H:CA7_SCU_LINE_ADDR_L

define CA7_SCU_L2_TAG_L log2(CA7_MIN_L2_SIZE/CA7_SCU_L2_ASSOC)
define CA7_SCU_L2_TAG_W (CA7_SCU_ADDR_W-log2(CA7_MIN_L2_SIZE/CA7_SCU_L2_ASSOC)) define CA7_SCU_L2_TAG_B CA7_SCU_ADDR_W-1:log2(CA7_MIN_L2_SIZE/CA7_SCU_L2_ASSOC)

define CA7_SCU_L2_TAGRAM_TAG_B 0+:CA7_SCU_L2_TAG_W
define CA7_SCU_L2_TAGRAM_NS_B CA7_SCU_L2_TAG_W
define CA7_SCU_L2_TAGRAM_OUTER_ATTRS_B (CA7_SCU_L2_TAG_W+1)+:2
define CA7_SCU_L2_TAGRAM_DIRTY_B (CA7_SCU_L2_TAG_W+3)
define CA7_SCU_L2_TAGRAM_CLSTR_UNIQ_B (CA7_SCU_L2_TAG_W+4)
define CA7_SCU_L2_TAGRAM_VALID_B (CA7_SCU_L2_TAG_W+5)+:2

define CA7_SCU_L2_TAGRAM_INVALID 2'b00 define CA7_SCU_L2_TAGRAM_VALID_INNER 2'b10
define CA7_SCU_L2_TAGRAM_VALID_OUTER 2'b01 define CA7_SCU_L2_TAGRAM_VALID_NS 2'b11

define CA7_SCU_L2_TAGRAM_OUTER_NC_B 2'b00 define CA7_SCU_L2_TAGRAM_OUTER_WT_NWA 2'b01
define CA7_SCU_L2_TAGRAM_OUTER_WB_NWA 2'b10 define CA7_SCU_L2_TAGRAM_OUTER_WB_WA 2'b11

define CA7_SCU_L2_WAY_W log2(`CA7_SCU_L2_ASSOC)

define CA7_SCU_L2_TAGRAM_ADDR_W CA7_SCU_L2_INDEX_W
define CA7_SCU_L2_TAGRAM_DATA_W (CA7_SCU_L2_TAG_W+7)

define CA7_SCU_L2_DATARAM_EN_W 8 define CA7_SCU_L2_DATARAM_ADDR_W (log2(CA7_MAX_L2_SIZE/CA7_SCU_LINE_LENGTH)) define CA7_SCU_L2_DATARAM_DATA_W (`CA7_SCU_LINE_LENGTH*8)

//-----------------------------------------------------------------------------
// External master AXI
//-----------------------------------------------------------------------------

define CA7_SCU_EXT_RID_W 6 define CA7_SCU_EXT_WID_W 5

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